With an increase in the density of an LSI and an improvement in performance of the LSI, a metal-insulator-semiconductor field-effect transistor (MISFET) has recently been miniaturized. Since a gate length is subjected to scaling, the problem with a short channel effect, which causes a reduction in a threshold voltage Vth, is troublesome. The short channel effect is attributable to the fact that spreading of a depletion layer located between a source and drain of an MISFET affects a channel portion due to a reduction in the length of a channel. One of methods for suppressing this effect is to increase an impurity concentration of the channel portion and suppress the spreading of the depletion layer located between the source and drain of the MISFET. When the impurity concentration of the channel portion is increased, however, a driving current is degraded depending on mobility (affected by an increase in the amount of scattered impurities) of carriers. In addition, the increased impurity concentration increases a parasitic capacity between a substrate and the source and a parasitic capacity between the substrate and the drain, which hinders the high-speed operation of the MISFET.
Traditionally, the threshold voltage Vth for the MISFET is controlled on the basis of an impurity concentration of a channel region. In an LSI formed in accordance with a design rule of approximately 100 nm node, channel impurity concentration is controlled in a relatively proper manner using an ion injection technique and a short-time thermal treatment technique.
For an MISFET formed in accordance with a design rule of 100 nm node or later, when a method for controlling a threshold voltage Vth on the basis of the amount of impurities in a channel is applied, an absolute number of impurities that contribute to a threshold voltage Vth for a single MISFET is reduced as the length of the channel is reduced. Thus, a variation in the threshold voltage Vth due to a statistic variation cannot be ignored (refer to Non-Patent Document 1). For a process to be performed on a fine device, it is requested to allow the work function of a gate electrode to control the threshold voltage Vth for the MISFET using the impurity concentration control of the channel portion and other methods.
To address the problems, a silicon-on-insulator (SOI) structure has attracted attention in recent years. Since shallow trench isolation is completely performed using an insulating film (for example, silicon oxide film) in the SOI structure, a soft error and a latch-up are suppressed, and even in a high-density LSI, high reliability can be obtained and the capacity of a junction of diffusion layers can be reduced. Thus, the amounts of charges to be accumulated and released due to switching are reduced. It is effective to operate with low power consumption at a high speed.
The SOI type MISFET mainly has two operation modes. One of the operation modes is a full depletion type SOI in which a depletion layer that is induced by a body region located immediately under the gate electrode reaches a bottom surface of the body region or a boundary with an embedded oxide film. The other of the operation modes is a partial depletion SOI in which the depletion layer does not reach the bottom surface of the body region and a neutral region remains.
In the full depletion type SOI MISFET, the thickness of the depletion layer located immediately under the gate electrode is limited by the embedded oxide film. Thus, the amount of charges in the depletion layer is much more reduced than the partial depletion type SOI MISFET. The amount of mobile charges that contribute to a drain current increases. As a result, advantageously a steep subthreshold characteristic (S characteristic) can be obtained.
When the steep S characteristic is obtained, the threshold voltage Vth can be reduced while an off-leak current is suppressed. As a result, the drain current is ensured with a low operation voltage. For example, the MISFET can be formed and operate with a voltage of 1 V or less (and a threshold voltage of 0.3 V or less). Thus, the MISFET can operate with remarkably low consumption power.
In addition, forming the MISFET on a normal substrate leads to the problem of the aforementioned short channel effect. In the full depletion type SOI MISFET, the substrate is separated from elements by the oxide film and the depletion layer does not spread. Thus, in the full depletion type SOI MISFET, the concentration of the substrate can be reduced. Thus, a reduction (caused by an increase in the amount of scattered impurities) in the mobility of carriers is suppressed. Therefore, a high driving current can be achieved.
In comparison with a method for controlling the threshold voltage Vth using an impurity concentration, a variation (caused by a statistic variation in the number of impurities) in the threshold voltage Vth for a single MISFET can be reduced.
Another conventional technique known for an SOI MISFET is a double gate MISFET structure. For example, the double gate MISFET structure has been proposed in Patent Document 1. In the aforementioned SOI MISFET, a source diffusion layer and a drain diffusion layer are formed in an SOI layer 105 using a dummy gate electrode and self-aligning. After that, a reversed pattern groove of the dummy gate electrode is formed. Then, an embedded gate is formed by injecting ions from the groove onto a supporting substrate 1. After that, a metal film such as W is embedded selectively in the aforementioned groove region to form an upper gate electrode. For improvement in the performance of the SOI MISFET, a double gate structure is an effective means. However, it is difficult to embed and form a high-concentration diffusion layer and the like in the supporting substrate provided with a double gate MISFET based on a currently known method without an adverse effect on the SOI layer. Thus, this structure is still not put into practical use.
When the difficulty in manufacturing is ignored and the essential concept of the double gate MISFET structure is taken into consideration, it is premised that the embedded gate is accurately aligned with the upper gate, and elements need to be individually arranged. Basically, there is no concept that a role of an embedded gate electrode is shared by a plurality of MISFETs. In an ultrafine SOI MISFET, alignment error of an embedded gate is fatal and leads directly to a variation in a parasitic capacity and a variation in the amount of a driving current. Thus, even when the parasitic capacity is effectively taken advantage of in order to stabilize a dynamic operation, stable use of the ultrafine SOI MISFET cannot be achieved as long as the variation in the capacity is not suppressed.
In addition, a threshold voltage for the double gate structure SOI MISFET is determined only on the basis of a work function of a material of the upper gate and a work function of a material of the embedded gate when a component of the SOI layer is excluded. Thus, it is not substantially possible to set a threshold voltage level for each of desired MISFETs. It is premised that the embedded gate electrode and the upper gate electrode are connected in a region located outside an MISFET active region or connected in a shallow trench isolation region, and consistency based on a layout of peripheral elements is essential.
In the full depletion type SOI MISFET formed with an SOI substrate in which an embedded insulating film has a thickness of 50 nm or less, preferably 10 nm or less and a thin monocrystalline semiconductor film has a thickness of 20 nm or less, when a gate potential is applied to a well diffusion layer located immediately under the SOI MISFET, the SOI MISFET is more conductive due to the high potential (of the well diffusion layer) applied through the thin embedded insulating film. Thus, the amount of the driving current can be significantly increased so that a high current is achieved. When the applied gate potential is a low potential, the potential of the well diffusion layer is reduced in response thereto. The SOI MISFET can quickly become nonconductive. In the aforementioned operation mode, the amount of the driving current can be more increased under the condition that causes the same amount of a leak current, and the SOI MISFET can be more quickly switched between the conductive state and the nonconductive state. Insulation and isolation of a side surface of the well diffusion layer contributes to a reduction in the parasitic capacity or a reduction in a delay (time constant) of a signal to be applied. In addition, as the thickness of the embedded insulating film is smaller, the embedded insulating film is more effective to increase the amount of the driving current. It is desirable that the thickness of the embedded insulating film be equal to the thickness of a gate insulating film of the SOI MISFET.
As described above, applying the thin embedded insulating film to the SOI MISFET allows the double gate structure to effectively and essentially improve the performance of the SOI MISFET. The well diffusion layer that is located immediately under the SOI MISFET is formed under the gate electrode in a self-aligned manner. Thus, problems with the double gate MISFET structure, which involve a variation (caused by a positional error of the embedded gate electrode) in the amount of the driving current and a variation in the parasitic capacity, can be essentially eliminated.
As described above, the SOI type MISFET exhibits features of low consumption power and high speed.